The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method of producing an overlay vernier with better alignment characteristics.
As design rule parameters of a semiconductor device decreases, it becomes more difficult to form an overlay vernier for performing an alignment process for each layer of a semiconductor device.
FIGS. 1a through 1d are cross-sectional diagrams illustrating a conventional method for forming an overlay vernier. The left side (i) represents an overlay vernier region, and the right side (ii) represents a gate formation process in a cell region. Both regions are formed simultaneously with (i) being a dummy region and (ii) being an active region.
Referring to FIG. 1a, a semiconductor substrate 10 is etched at a predetermined thickness to form a recess gate region(or a trench) 15. Simultaneously, an overlay vernier(or a trench) 25 is formed.
Referring to FIG. 1b, a gate oxide film 20 having a predetermined thickness is formed over the entire surface of the semiconductor substrate 10.
Referring to FIG. 1c, a gate polysilicon layer 30 which fills the recess gate region 15 and the overlay vernier region 25 is formed. The surface of the gate polysilicon layer 30 a concave shape (or depression) due to the step difference of the recess gate and overlay vernier regions 15 and 25 to their surrounding structures.
Referring to FIG. 1d, a gate metal layer (or a gate conductive layer) 40 and a gate hardmask layer 50 are sequentially formed over the gate polysilicon layer 30. The gate hardmask layer 50, the gate metal layer 40 and the gate polysilicon layer 30 of the cell region are patterned to form a gate. When the gate polysilicon layer 30 is formed, the step difference of the overlay vernier region 25 becomes less prominent, and the left and right edge of the overlay vernier region 25 may become unsymmetrical so that the alignment process becomes difficult to perform.
FIGS. 2a and 2b are cross-sectional images illustrating the conventional overlay vernier region.
According to the conventional method for manufacturing a semiconductor device, when the gate polysilicon layer is formed, the step difference of the overlay vernier is not as deep and the sides are gently sloped. This can make the alignment marks unclear (see FIG. 2a). The sides of the step difference of the overlay vernier can become unsymmetrical (see region (a) of FIG. 2b). As a result, overlay characteristics are degraded and yield is reduced.